1. Field of the Invention
This invention relates to an error correction/detection circuit for correcting/detecting bit errors with respect to bit data, and to a semiconductor memory device in which the error correction/detection circuit is used.
2. Description of the Related Art
Two methods, i.e., parallel processing scheme (IEEE Journal of Solid-State Circuit, vol. 24, pp 50, 1989) and serial processing scheme ("Error-Correcting Codes" authored by Peterson and Weldon, second edition) are known as error correction/detection methods. FIGS. 1A and 1B illustrate constitutional examples of a 1 bit error correction code with respect to data of 512 bit depth.times.8 bit width in parallel processing scheme and serial processing schemes, respectively.
In a conventional semiconductor memory device, since an error correction processing time has been considered to be the highest priority, parallel processing scheme (FIG. 1A) which exhibits less generation of check bits in case of writing operation as well as less time loss for correcting errors in case of reading operation at the time of inputting/outputting data has been utilized. In this case, 4 bits of check bit are required for 8 bit data. In other words, its memory region increases by 50%. On the other hand, in case of serial processing scheme (FIG. 1B), 10 bits of check bit are sufficient for 512 bit data, and the redundancy thereof is about 2%. However, a delay time of 522 bit length is required for correcting errors.
Serial processing scheme is more suitable than parallel processing scheme, provided that the reliability of a memory in case of adding no error correcting code is inferior to that to be required, and the reliability of a memory in case of adding a code for correcting 1 bit error in 512 bit data is better than that to be required, besides a rate of increase in a memory region is made more preferential than a processing time for error correction.
In a size of error correction circuit, however, there is a case where serial processing scheme becomes conversely larger than parallel processing scheme. The reason why there is the above case is as follows. In case of serial processing scheme, the error correction circuit comprises principally a delay circuit composed of shift registers equal to the depth of data including a check data section (522 bits.times.8 sets in the above example) and a syndrome generating circuit composed of shift registers the number of which is equal to the check bit number (10 bits.times.8 sets in the above example), while in parallel processing scheme, the error correction circuit comprises only 4 sets of 5 input exclusive ORs and their output logics.
As is understood from the above description, while serial processing scheme can reduce extremely a rate of increase in the memory region as compared with that of parallel processing scheme, the size of an error correction circuit becomes conversely larger, so that an effect for suppressing a rate of increase in memory chips is small.
Furthermore, in parallel processing scheme, since it is required to effect processing in accordance with 8 bit parallel manner, the error correction circuit must be disposed either between a memory cell and a bit line control circuit or in a place where all of IO lines are gathered, so that flexibility in the arrangement is poor from a layout point of view.
Constitutions and problems of conventional error correction/detection circuits will be specifically described hereinbelow.
FIG. 2 is a block diagram showing the error correction/detection circuit according to a first conventional example which is disclosed in the above-mentioned literature ("Error-Correcting Codes" authored by Peterson and Weldon, Second Edition).
Input data is input to a syndrome generating circuit (check bit generation circuit) 1 and a delay circuit 4. The syndrome has a certain value, i.e., zero in the case where the input data contain no error, while a number other than zero in the case where the input data contain an error, and the resulting value is input to an error position/size calculating circuit 2 which calculates the position and the size of an error.
In the case where the input syndrome is zero, the error position/size calculating circuit 2 outputs zero, and the data input to the delay circuit 4 are output through the error correction circuit 3 as they are without any modification. When the syndrome has a certain value being the one other than zero, the error position/size calculating circuit 2 calculates the position and the size of the error, and the error involved in the data input to the delay circuit 4 is corrected in the error correction circuit 3, thereafter the data corrected are output therefrom. More specifically, correction of errors is made by the error correction circuit 3 in only the case where there is outputting data involving any error, and as a result correct data are output.
In this type of constitution, however, the delay circuit 4 is composed of shift registers each having the same length as that of input data, so that a ratio of the delay circuit 4 occupying the whole error correction circuit becomes high in case of particularly a long code length. This results in a cause for increasing the size of an error correction circuit.
In the following, a second conventional example relating to a so-called 1 byte error correction code wherein 1 byte error is corrected among information data of (2.sup.b -3) bytes in which 1 byte is composed of b bits will be described. In a single byte error correction circuit, check data of 2 bytes are prepared from input information data (coding), and an error of 1 byte is corrected from information data and check data (decoding), so that correct information data are output.
In the meantime, the maximum data length is limited to (2.sup.b -3) due to magnitude b of 1 byte, so that when longer information data than (2.sup.b -3) bytes are intended to be handled, the information data must be divided into blocks each having a length of (2.sup.b -3) or less. In the case where information data are successively input to an error correction circuit, it is required to prepare a single byte error correction circuit with respect to each of the blocks. For this reason, the size of such error correction circuit becomes large. This case is the same as a plural byte error check circuit.
Furthermore, in the case where there is only a single error correction circuit, information is coded/decoded in every block of information data, so that the information data cannot be successively input to or output from the error correction circuit.
FIG. 3 is a block diagram showing a semiconductor memory device provided with the error correction/detection circuit relating to a third conventional example. The semiconductor memory device 13 comprises a memory cell array 6 in which electrically rewritable memory cells are arranged in matrix-shaped, a sense amplifier/data latch circuit 8 which latches data in memory cells in the memory cell array or rewritten data, a plurality of data input/output buffers 12 which input rewritten data from the outside and output data read from the memory cells, an error correction/detection circuit 11 which generates check data for correcting and detecting an error from the rewritten data input as well as which corrects and detects an error in read data from the read data and check data in case of outputting the read data, an address buffer 10 to which are input addresses of the memory cells and from which are output column addresses and row addresses, a column decoder 9 which decodes column addresses and controls inputting/outputting of data from the sense amplifier/data latch circuit 8, a row decoder 7 which decodes row addresses, and a writing/reading control circuit 5 which outputs control signals for writing and reading data in the memory cells.
The semiconductor memory device 13 as described above is disclosed in the above-mentioned literature (IEEE Journal of Solid-State Circuits, vol. 24, pp 50, 1989). In the present conventional example, for the sake of minimizing a processing time for coding/decoding data, error correction codes are processed parallely. The code consists of information data of 1 bit or plural bits in every data input/output lines and check data obtained from the information data, since to the code is applicable parallel processing.
In every case where the bit number of information data doubles, the bit number of check data requires about 1 more bit, so that a ratio of the bit number of check data to that of information data decreases with increase of the bit number of information data. On the other hand, the number of an exclusive OR for coding/decoding is roughly proportional to the bit number of information data, so that the size of a coding/decoding circuit becomes large with increase of the bit number of information data. Accordingly, there is the minimum value of a sum of an area of redundant memory cells and an area of a coding/decoding circuit for effecting error correction/detection, and further there is an optimum value of the bit number in information data which brings about the aforesaid minimum value.
On one hand, in error correction/detection circuits, such a type of circuit is realized by shift register series instead of the above described type of circuit which is realized by exclusive OR. In the former case, it is required to prepare a delay circuit which is realized by shift register series the number of which is equal to the bit number of check data and shift register series the number of which is equal to the sum of the bit number of information data and the bit number of check data. Therefore, the number of shift registers increases about 2 bits in every case where the bit number of information data becomes twice. For this reason, although the size of a coding/decoding circuit per unit information data reduces with increase of the bit number of information data, a ratio of delay circuits occupying the whole of an error correction circuit becomes high, and this brings about an increase in the size of an error correction circuit. Moreover, when this type of an error correction/detection circuit is used, a delay time being proportional to the sum of the bit number of information data and the bit number of check data is required for decoding.
Furthermore, a layout of the memory cell array 6, the respective circuits 8, 11, 12, input/output pads 100 and the like in the present conventional example is shown in FIG. 4. As is seen from the figure, the error correction/detection circuit 11 is required to be disposed between the memory cell array 6 and the sense amplifier/data latch circuit 8, or in a place where the whole I/O lines are collected, so that there is no flexibility from a layout point of view.
There is such a case even when burst error occurs, the data become code words, so that the burst error cannot be detected. More specifically, when a burst error occurs, all of the "1" in the data turn into "0", so that the whole "0" data composed of all the "0" values is judged in such a way that there is no error because the whole "0" data is one of the code words. Thus, the occurrence of burst error cannot be detected in this case.
As described above, in a conventional error correction/detection circuit of serial processing scheme, a ratio of the delay circuit occupying the whole error correcting circuit becomes high in case of a long code length, and this results in an increase in the size of the error correction circuit.
Furthermore, when there is only a single byte error correction circuit, information data cannot be input/output successively. Accordingly, when information data are successively input to the error correction circuit, single byte error correction circuits become required for each of blocks, so that the size of the error correction circuit comes large.
Moreover, in an error correction circuit of the type which is realized by shift register series, a ratio of the delay circuit occupying the whole error correction circuit becomes high in case of particularly long code length, and this brings about an increase in the size of the error correction circuit.
Still further, an error correction/detection circuit is required to be disposed either between the memory cell array and the data circuit, or in a place where the whole IO lines are gathered, so that this creates a problem that there is reduced flexibility from a layout point of view.